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ultralow distortion, differential adc driver ADA4937-1 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features extremely low harmonic distortion ?112 dbc hd2 @ 10 mhz ?79 dbc hd2 @ 70 mhz ?70 dbc hd2 @ 100 mhz ?102 dbc hd3 @ 10 mhz ?91 dbc hd3 @ 70 mhz ?84 dbc hd3 @ 100 mhz low input voltage noise: 2.2 nv/hz high speed ?3 db bandwidth of 1.9 ghz, g = 1 slew rate: 6000 v/s, 25% to 75% 0.1 db gain flatness to 200 mhz fast overdrive recovery of 1 ns 1 mv typical offset voltage externally adjustable gain differential-to-differential or single-ended-to-differential operation adjustable output common-mode voltage single-supply operation: 3.3 v to 5 v pb-free, 3 mm 3 mm 16-lead lfcsp applications adc drivers single-ended-to-differential converters if and baseband gain blocks differential buffers line drivers functional block diagram 06591-001 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +ou t 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ADA4937-1 figure 1. ? 55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 11 01 0 distortion (dbc) frequency (mhz) 0 hd2, v s = 5.0v hd3, v s = 5.0v hd2, v s = 3.3v hd3, v s = 3.3v 06591-002 figure 2. harmonic distortion vs. frequency general description the ADA4937-1 is a low noise, ultralow distortion, high speed differential amplifier. it is an ideal choice for driving high performance adcs with resolutions up to 16 bits from dc to 100 mhz. the adjustable level of the output common mode allows the ADA4937-1 to match the input of the adc. the internal common-mode feedback loop also provides exceptional output balance as well as suppression of even-order harmonic distortion products. with the ADA4937-1, differential gain configurations are easily realized with a simple external feedback network of four resistors determining the closed-loop gain of the amplifier. the ADA4937-1 is fabricated using analog devices, inc. proprietary silicon-germanium (sige), complementary bipolar process, enabling it to achieve very low levels of distortion with an input voltage noise of only 2.2 nv/hz. the low dc offset and excellent dynamic performance of the ADA4937-1 make it well suited for a wide variety of data acquisition and signal processing applications. the ADA4937-1 is available in a pb-free, 3 mm 3 mm 16-lead lfcsp. the pinout has been optimized to facilitate pcb layout and minimize distortion. the part is specified to operate over the ?40c to +105c temperature range for 3.3 v supplies and the ?40c to +85c temperature range for 5 v supplies.
ADA4937-1 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v operation ............................................................................... 3 3.3 v operation ............................................................................ 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 test circ u its ..................................................................................... 16 operational description ................................................................ 17 definition of terms .................................................................... 17 theory of operation ...................................................................... 18 analyzing an application circuit ............................................ 18 setting the closed-loop gain .................................................. 18 estimating the output noise voltage ...................................... 18 the impact of mismatches in the feedback networks ......... 19 calculating the input impedance of an application circuit 19 input common-mode voltage range in single-supply applications ................................................................................ 19 setting the output common-mode voltage .......................... 19 layout, grounding, and bypassing .............................................. 21 high performance adc driving ................................................. 22 3.3 v operation .......................................................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 5/07revision 0: initial version
ADA4937-1 rev. 0 | page 3 of 28 specifications 5 v operation t a = 25c, +v s = 5 v, ?v s = 0 v, v ocm = +v s /2, r t = 61.9 , r g = r f = 200 , g = 1, r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 1. d in to out performance parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 1900 mhz bandwidth for 0.1 db flatness v out, dm = 0.1 v p-p 200 mhz large signal bandwidth v out, dm = 2 v p-p 1700 mhz slew rate v out, dm = 2 v p-p; 25% to 75% 6000 v/s overdrive recovery time v in = 0 v to 1.5 v step; g = 3.16 <1 ns noise/harmonic performance see figure 45 for distortion test circuit second harmonic v out, dm = 2 v p-p; 10 mhz ?112 dbc v out, dm = 2 v p-p;, 70 mhz ?79 dbc v out, dm = 2 v p-p; 100 mhz ?70 dbc third harmonic v out, dm = 2 v p-p; 10 mhz ?102 dbc v out, dm = 2 v p-p; 70 mhz ?91 dbc v out, dm = 2 v p-p; 100 mhz ?84 dbc imd f 1 = 70 mhz; f 2 = 70.1 mhz; v out, dm = 2 v p-p ?91 dbc voltage noise (rti) f = 100 khz 2.2 nv/hz input current noise f = 100 khz 3 pa/hz noise figure g = 4; r t = 136 ; r f = 200 ; r g = 37 ; f = 100 mhz 15 db input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v din? = 2.5 v ?2.5 +0.5 +2.5 mv t min to t max variation 1 v/c input bias current ?30 ?20 ?10 a t min to t max variation 0.01 a/c input offset current ?2 +0.5 +2 a input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage 0.3 to 3.0 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1 v ?67 ?80 db output characteristics output voltage swing maximum ?v out ; single-ended output; r f = r g = 10 k 0.8 4.2 v linear output current >100 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v; 10 mhz; see figure 44 for test circuit ?61 db
ADA4937-1 rev. 0 | page 4 of 28 table 2. v ocm to out performance parameter conditions min typ max unit v ocm dynamic performance ?3 db bandwidth 440 mhz slew rate v in = 1.5 v to 3.5 v; 25% to 75% 1150 v/s input voltage noise (rti) f = 100 khz 7.5 nv/hz v ocm input characteristics input voltage range 1.2 3.8 v input resistance 8 10 12 k input offset voltage v os, cm = v out, cm ; v din+ = v dinC = +v s /2 2 6.1 mv input bias current 0.5 a v ocm cmrr v out, dm /v ocm ; v ocm = 1 v ?75 db gain v out, cm /v ocm ; v ocm = 1 v 0.97 0.98 1.00 v/v power supply operating range 3.0 5.25 v quiescent current 38.5 39.5 41.0 ma t min to t max variation 17 a/c powered down 0.02 0.3 0.4 ma power supply rejection ratio v out, dm /v s ; v s = 1 v ?70 ?90 db power down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 1 s turn-on time 200 ns pd bias current enabled pd = 5 v 10 40 50 a disabled pd = 0 v ?300 ?200 ?150 a operating temperature range ?40 +85 c
ADA4937-1 rev. 0 | page 5 of 28 3.3 v operation t a = 25c, +v s = 3.3 v, ?v s = 0 v, v ocm = +v s /2, r t = 61.9 , r g = r f = 200 , g = 1, r l, dm = 1 k, unless otherwise noted. all specifications refer to single-ended input and differential outputs, unless otherwise noted. table 3. d in to out performance parameter conditions min typ max unit dynamic performance ?3 db small signal bandwidth v out, dm = 0.1 v p-p 1900 mhz bandwidth for 0.1 db flatness v out, dm = 0.1 v p-p 200 mhz large signal bandwidth v out , dm = 2 v p-p 1300 mhz slew rate v out, dm = 2 v p-p; 25% to 75% 4000 v/s overdrive recovery time v in = 0 v to 1.0 v step; g = 3.16 <1 ns noise/harmonic performance see figure 45 for distortion test circuit second harmonic v out, dm = 2 v p-p; 10 mhz ?106 dbc v out, dm = 2 v p-p; 70 mhz ?88 dbc v out, dm = 2 v p-p; 100 mhz ?81 dbc third harmonic v out, dm = 2 v p-p; 10 mhz ?93 dbc v out, dm = 2 v p-p; 70 mhz ?80 dbc v out, dm = 2 v p-p; 100 mhz ?71 dbc imd f 1 = 70 mhz; f 2 = 70.1 mhz; v out , dm = 2 v p-p ?87 dbc voltage noise (rti) f = 100 khz 2.2 nv/hz input current noise f = 100 khz 3 pa/hz noise figure g = 4; r t = 136 ; r f = 200 ; r g = 37 ; f = 100 mhz 15 db input characteristics offset voltage v os, dm = v out, dm /2; v din+ = v din? = +v s /2 ?2.5 +0.5 +2.5 mv t min to t max variation 1 v/c input bias current ?50 ?20 ?10 a t min to t max variation 0.01 a/c input resistance differential 6 m common mode 3 m input capacitance 1 pf input common-mode voltage 0.3 to 1.2 v cmrr ?v out, dm /?v in, cm ; ?v in, cm = 1.0 v ?67 ?80 db output characteristics output voltage swing maximum ?v out ; single-ended output 0.8 2.5 v linear output current 95 ma output balance error ?v out, cm /?v out, dm ; ?v out, dm = 1 v; f = 10 mhz; see figure 44 for test circuit ?61 db
ADA4937-1 rev. 0 | page 6 of 28 table 4. v ocm to out performance parameter conditions min typ max unit v ocm dynamic performance ?3 db bandwidth 440 mhz slew rate v in = 0.9 v to 2.4 v; 25% to 75% 900 v/s input voltage noise (rti) f = 100 khz 7.5 nv/hz v ocm input characteristics input voltage range 1.2 2.1 v input resistance 10 k input offset voltage v os, cm = v out, cm ; v din+ = v din? = 1.67 v 2 6.1 mv input bias current 0.5 a v ocm cmrr ?v out, dm /?v ocm ; ?v ocm = 1 v ?75 db gain ?v out, cm /?v ocm ; ?v ocm = 1 v 0.97 0.98 1.00 v/v power supply operating range 3.0 5.25 v quiescent current 36 38 39 ma t min to t max variation 17 a/c powered down 0.02 0.2 0.3 ma power supply rejection ratio ?v out, dm /?v s ; ?v s = 1 v ?70 ?90 db power down ( pd ) pd input voltage powered down 1 v enabled 2 v turn-off time 1 s turn-on time 200 ns pd bias current enabled pd = 3.3 v 10 20 30 a disabled pd = 0 v ?200 ?120 ?100 a operating temperature range ?40 +105 c
ADA4937-1 rev. 0 | page 7 of 28 absolute maximum ratings table 5. parameter rating supply voltage 5.5 v power dissipation see figure 3 storage temperature range ?65c to +125c operating temperature range ?40c to +105c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in eia/jesd 51-7. table 6. thermal resistance package type ja unit 16-lead lfcsp (exposed pad) 95 c/w maximum power dissipation the maximum safe power dissipation in the ADA4937-1 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4937-1. exceeding a junction temperature of 150c for an extended period can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to the load drive depends upon the particular application. the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads/exposed pad from metal traces, through holes, ground, and power planes reduces the ja . figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 16-lead lfcsp (95c/w) on a jedec standard 4-layer board. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?45 1059585 75 655545352515 5 ?5 ?15?25?35 maximum power dissipation (w) ambient temperature (c) 06591-003 figure 3. maximum power dissipation vs. temperature for a 4-layer board esd caution
ADA4937-1 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 06591-400 1 ?fb 2 +in 3 ?in 4 +fb 11 ?out 12 pd 10 +out 9v ocm 5 + v s 6 + v s 7 + v s 8 + v s 1 5 ? v s 1 6 ? v s 1 4 ? v s 1 3 ? v s ADA4937-1 top view (not to scale) pin 1 indicator figure 4. pin configuration table 7. pin function descriptions pin no. mnemonic description 1 ?fb negative output for feedback component connection. 2 +in positive input summing node. 3 ?in negative input summing node. 4 +fb positive output for feedback component connection. 5 to 8 +v s positive supply voltage. 9 v ocm output common-mode voltage. 10 +out positive output for load connection. 11 ?out negative output for load connection. 12 pd power-down pin. 13 to 16 ?v s negative supply voltage.
ADA4937-1 rev. 0 | page 9 of 28 typical performance characteristics t a = 25c, +v s = 5 v, ?v s = 0 v, v out, dm = 2 v p-p, v ocm = +v s /2, r t = 61.9 , r g = r f = 200 , g = 1, r l, dm = 1 k, unless otherwise noted. refer to figure 43 for test setup. 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) g = +1 g = +2 g = +5 06591-004 figure 5. small signal frequency response for various gains, v out, dm = 100 mv p-p 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) 06591-005 v s = 3.3v v s = 5.0v figure 6. small signal frequency response for various supplies, v out, dm = 100 mv p-p 6 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) +25c +105c ?40c 06591-006 figure 7. small signal frequency response for various temperatures, v out, dm = 100 mv p-p 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) g = +1 g = +2 g = +5 06591-007 figure 8. large signal frequency response for various gains 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) 06591-008 v s = 3.3v v s = 5.0v figure 9. large signal frequency response for various supplies 6 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) +25c +105c ?40c 06591-009 figure 10. large signal frequency response for various temperatures
ADA4937-1 rev. 0 | page 10 of 28 6 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 100 ? r l = 200 ? 06591-010 figure 11. small signal frequency response for various loads, v out, dm = 100 mv p-p 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) v s = 3.3v, g = +1 v s = 3.3v, g = +2 v s = 3.3v, g = +5 06591-011 figure 12. small signal frequency response for various gains, v s = 3.3 v and v out, dm = 100 mv p-p 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) g = +1 g = +2 g = +5 06591-012 figure 13. small signal frequency response for various gains, v out, dm = 100 mv p-p, r f = 348 6 ?9 ?6 ?3 0 3 1 10 100 1000 closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 100 ? r l = 200 ? 06591-013 figure 14. large signal frequency response for various loads 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) v s = 3.3v, g = +1 v s = 3.3v, g = +2 v s = 3.3v, g = +5 06591-014 figure 15. large signal frequency response for various gains, v s = 3.3 v 6 ?15 ?12 ?9 ?6 ?3 0 3 1 10 100 1000 normalized closed-loop gain (db) frequency (mhz) g = +1 g = +2 g = +5 06591-015 figure 16. large signal frequency response for various gains, r f = 348
ADA4937-1 rev. 0 | page 11 of 28 3 ?12 ?9 ?6 ?3 0 1 10 100 1000 v ocm closed-loop gain (db) frequency (mhz) v ocm = 1.0v v ocm = 2.5v v ocm = 3.9v 06591-017 figure 17. small signal frequency response for various v ocm 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.4 0.3 0.2 1 10 100 closed-loop gain (db) frequency (mhz) r l = 1k ? r l = 100 ? r l = 200 ? 06591-018 figure 18. 0.1 db flatness response for various loads ? 55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 ?110 ?115 11 01 0 distortion (dbc) frequency (mhz) 0 hd2, v s = 5.0v hd3, v s = 5.0v hd2, v s = 3.3v hd3, v s = 3.3v 06591-020 figure 19. harmonic distortion vs. frequency and supply voltage ? 50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 11 01 0 distortion (dbc) frequency (mhz) 0 hd2, g = +1, r f = 200 ? hd3, g = +1, r f = 200 ? hd2, g = +2, r f = 402 ? hd3, g = +2, r f = 402 ? 06591-021 figure 20. harmonic distortion vs. frequency and gain ? 50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 11 01 0 distortion (dbc) frequency (mhz) 0 hd2, r l = 1k ? hd3, r l = 1k ? hd2, r l = 200 ? hd3, r l = 200 ? 06591-022 figure 21. harmonic distortion vs. frequency and load ? 50 ?60 ?70 ?80 ?90 ?100 ?110 ?130 ?120 ?1 7 6543210 distortion (dbc) v out (v) hd2, v s = 3.3v hd3, v s = 3.3v hd2, v s = 5.0v hd3, v s = 5.0v 06591-023 figure 22. harmonic distortion vs. v out and supply voltage
ADA4937-1 rev. 0 | page 12 of 28 ? 30 ?50 ?40 ?60 ?70 ?80 ?90 ?100 ?110 ?120 1.0 4.0 3.5 3.0 2.5 2.0 1.5 distortion (dbc) v ocm (v) hd2, f = 10mhz hd3, f = 10mhz hd2, f = 75mhz hd3, f = 75mhz 06591-025 figure 23. harmonic distortion vs. v ocm and frequency ? 40 ?50 ?60 ?70 ?80 ?90 ?100 1.1 2.01.9 1.8 1.71.61.5 1.4 1.31.2 distortion (dbc) v ocm (v) hd2, f = 30mhz hd3, f = 30mhz hd2, f = 75mhz hd3, f = 75mhz 06591-045 figure 24. harmonic distortion vs. v ocm and frequency, v s = 3.3 v ? 50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 11 01 0 distortion (dbc) frequency (mhz) 0 hd2, 1v p-p hd3, 1v p-p hd2, 2v p-p hd3, 2v p-p 06591-044 figure 25. harmonic distortion vs. frequency and v out , v s = 3.3 v 0 ?120 ?100 ?80 ?60 ?40 ?20 69.4 69.6 70.6 70.4 70.2 70.0 69.8 distortion (dbc) frequency (mhz) 06591-027 figure 26. 70 mhz intermodulation distortion ? 30 ?70 ?60 ?50 ?40 11 100 10 cmrr (db) frequency (mhz) 06591-059 k r l = 200 ? figure 27. cmrr vs. frequency ? 10 ?60 ?70 ?60 ?30 ?20 1 10 100 1000 output balance (db) frequency (mhz) 06591-029 r l = 200 ? figure 28. output balance vs. frequency
ADA4937-1 rev. 0 | page 13 of 28 ? 30 ?100 ?90 ?80 ?70 ?50 ?40 ?60 1 10 100 1000 psrr (db) frequency (mhz) v out, dm psrr, v s = 3.3v v out, dm psrr, v s = 5.0v 06591-030 figure 29. psrr vs. frequency, r l = 200 0 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 1 10 100 1000 s-parameters (db) frequency (mhz) s22 s11 06591-031 figure 30. return loss (s 11 , s 22 ) vs. frequency ? 55 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 1 10 100 distortion (dbc) frequency (mhz) sfdr, r l = 200 ? sfdr, r l = 1k ? 06591-032 figure 31. spurious-free dynamic range vs. frequency and load 28 10 12 14 16 18 20 22 24 26 10 100 noise figure (db) frequency (mhz) g = +2 g = +4 g = +1 06591-033 figure 32. noise fi gure vs. frequency 3 ?3 ?2 ?1 0 2 1 v out differential (v) time (2ns/div) 06591-060 figure 33. overdrive recove ry time (pulse input) 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 0 600 500 400 300 200 100 signal level (v) time (ns) 06591-034 v out diff v in 3 figure 34. overdrive amplitude char acteristics (trian gle wave input)
ADA4937-1 rev. 0 | page 14 of 28 60 0 5 10 15 20 25 30 35 40 45 50 55 1.0 2.01.91.81.71.61.5 1.3 1.4 1.21.1 supply current (ma) power-down voltage (v) +105c +55c +25c 0c ?40c 06591-036 figure 35. supply current vs. pd for various temperatures 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.15 0.10 voltage (v) time (1ns/div) 06591-039 figure 36. small signal pulse response 2.60 2.40 2.42 2.44 2.46 2.48 2.50 2.52 2.54 2.58 2.56 voltage (v) time (2ns/div) 06591-042 figure 37. small signal v ocm pulse response 60 0 5 10 15 20 25 30 35 40 45 50 55 1.0 2.01.91.81.71.61.5 1.3 1.4 1.21.1 supply current (ma) power-down voltage (v) +105c +55c +25c 0c ?40c 06591-037 figure 38. supply current vs. pd for various temperatures, v s = 3.3 v 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 voltage (v) time (1ns/div) v out, dm = 4v p-p v out, dm = 2v p-p 06591-040 figure 39. large signal pulse response 4.00 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.25 3.75 3.00 3.50 voltage (v) time (2ns/div) 06591-041 figure 40. large signal v ocm pulse response
ADA4937-1 rev. 0 | page 15 of 28 2.4 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 voltage (v) time (150ns/div) pd input single output 06591-038 figure 41. pd response vs. time 100 1 10 10 10m 1m 100k 10k 1k 100 input voltage noise (nv/ hz) frequency (hz) 06591-061 figure 42. voltage spectral noise density, rti
ADA4937-1 rev. 0 | page 16 of 28 test circuits 06591-046 ADA4937-1 1k ? 5v 200? 200 ? 50? 200 ? 27.5 ? 200? v ocm 61.9 ? v in figure 43. equivalent basic test circuit 06591-047 ADA4937-1 5v 200? 200 ? 50? 200 ? 50? 50? 27.5 ? 200? v ocm 61.9 ? v in figure 44. test circuit for output balance 06591-048 ADA4937-1 5v 200? 200 ? 50? 200 ? 412? 412? 27.5 ? 200? v ocm 61.9 ? v in filter 0.1f 0.1f filter figure 45. test circuit for distortion measurements
ADA4937-1 rev. 0 | page 17 of 28 operational description definition of terms 06591-051 ADA4937-1 +in ?in +out ?out +d in ? fb +fb ?d in v ocm r g r f r g v out, dm r l, dm r f figure 46. circuit definitions differential voltage is refers to te difference etween two node oltages or example te output differential oltage or euialentl output differential-mode oltage is defined as v out, dm v +out ? v ?out ere v +out and v ?out reer to te voltae at te +out and ?out terminal it repect to a common reerence common-mode voltage is refers to te aerage of two node oltages e output common-mode oltage is defined as v out, cm v +out + v ?out /2 balance balance is a measure of ow well differential signals are matced in amplitude and are exactl apart in pase balance is most easil determined placing a well-matced resistor diider etween te differential oltage nodes and comparing te magnitude of te signal at te diiders midpoint wit te magnitude of te differential signal see igure b tis definition output alance is te magnitude of te output common-mode oltage diided te magnitude of te output differential mode oltage dmout cmout v v error balance output , , =
ADA4937-1 rev. 0 | page 18 of 28 theory of operation the ADA4937-1 differs from conven tional op amps in that it has two outputs whose voltages move in opposite directions. like an op amp, it relies on open-loop gain and negative feedback to force these outputs to the desired voltages. the ADA4937-1 behaves much like a standard voltage feedback op amp and makes it easier to perform single-ended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. also like an op amp, the ADA4937-1 has high input impedance and low output impedance. two feedback loops are employed to control the differential and common-mode output voltages. the differential feedback, set with external resistors, controls only the differential output voltage. the common-mode feedback controls only the common- mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value. it is forced, by internal common-mode feedback, to be equal to the voltage applied to the v ocm input, without affecting the differential output voltage. the ADA4937-1 architecture results in outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. the common-mode feedback loop forces the signal component of the output common- mode voltage to zero. this results in nearly perfectly balanced differential outputs that are identical in amplitude and are exactly 180 apart in phase. analyzing an application circuit the ADA4937-1 uses open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. the differential error voltage is defined as the voltage between the differential inputs labeled +in and ?in (see figure 46 ). for most purposes, this voltage can be assumed to be zero. similarly, the difference between the actual output common-mode voltage and the voltage applied to v ocm can also be assumed to be zero. starting from these two assumptions, any application circuit can be analyzed. setting the closed-loop gain the differential-mode gain of the circuit in figure 46 can be determined by g f dmin dmout r r v v = , , this assumes the input resistors ( r g ) and feedback resistors ( r f ) on each side are equal. estimating the output noise voltage the differential output noise of the ADA4937-1 can be estimated using the noise model in figure 47 . the input- referred noise voltage density, v nin , is modeled as a differential input, and the noise currents, i nin? and i nin+ , appear between each input and ground. the noise currents are assumed to be equal and produce a voltage across the parallel combination of the gain and feedback resistances. v ncm is the noise voltage density at the v ocm pin. each of the four resistors contributes (4ktr x ) 1/2 . tabl e 8 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. 06591-067 ADA4937-1 + r f2 v nod v ncm v ocm v nin r f1 r g2 r g1 v nrf1 v nrf2 v nrg1 v nrg2 i nin+ i nin? figure 47. ADA4937-1 noise model table 8. output noise voltag e density calculations input noise contribution input noise term input noise voltage density output multiplication factor output noise voltage density term differential input v nin v nin g n v no1 = g n (v nin ) inverting input i nin? i nin? (r g2 ||r f2 ) g n v no2 = g n [i nin? (r g2 ||r f2 )] noninverting input i nin+ i nin+ (r g1 ||r f1 ) g n v no3 = g n [i nin+ (r g1 ||r f1 )] v ocm input v ncm v ncm g n ( 1 ? 2 ) v no4 = g n ( 1 ? 2 )(v ncm ) gain resistor r g1 v nrg1 (4ktr g1 ) 1/2 g n (1 ? 2 ) v no5 = g n (1 ? 2 )(4ktr g1 ) 1/2 gain resistor r g2 v nrg2 (4ktr g2 ) 1/2 g n (1 ? 1 ) v no6 = g n (1 ? 1 )(4ktr g2 ) 1/2 feedback resistor r f1 v nrf1 (4ktr f1 ) 1/2 1 v no7 = (4ktr f1 ) 1/2 feedback resistor r f2 v nrf2 (4ktr f2 ) 1/2 1 v no8 = (4ktr f2 ) 1/2
ADA4937-1 rev. 0 | page 19 of 28 ) similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the input- referred terms at +in and ?in by the appropriate output factor, where: ( 21 n | g + = 2 is the circuit noise gain. g1 f1 g1 1 rr r + = and g2 f2 g2 2 rr r + = are the feedback factors. when r f1 /r g1 = r f2 /r g2 , then 1 = 2 = , and the noise gain becomes g f n r r g +== 1 1 note that the output noise from v ocm goes to zero in this case. the total differential output noise density, v nod , is the root-sum- square of the individual output noise terms. = = 8 1i 2 noi nod vv the impact of mismatch es in the feedback networks as previously mentioned, even if the external feedback networks (r f /r g ) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. the amplitudes of the signals at each output remain equal and 180 out of phase. the input-to-output, differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. as well as causing a noise contribution from v ocm , ratio matching errors in the external resistors result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. in addition, if the dc levels of the input and output common- mode voltages are different, matching errors result in a small differential-mode output offset voltage. when g = 1, with a ground referenced input signal and the output common-mode level set to 2.5 v, an output offset of as much as 25 mv (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. resistors of 1% tolerance result in a worst- case input cmrr of about 40 db, a worst-case differential- mode output offset of 25 mv due to 2.5 v level-shift, and no significant degradation in output balance error. calculating the input impedance of an application circuit the effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. for balanced differential input signals, as shown in figure 48 , the input impedance (r in, dm ) between the inputs (+d in and ?d in ) is simply r in, dm = 2 r g . 06591-062 +v s ADA4937-1 +in ?in r f r f +d in ?d in v ocm r g r g v out, dm figure 48. ADA4937-1 configured for balanced (differential) inputs for an unbalanced, single-ended input signal (see figure 49 ), the input impedance is () ? ? ? ? ? ? ? ? ? ? ? ? + ? = f g f g cmin rr r r r 2 1 , r t r s 06591-063 ADA4937-1 +v s r f r g r s r g r f v ocm r t v out, dm figure 49. ADA4937-1 configured fo r unbalanced (single-ended) input the input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor r g . input common-mode voltage range in single-supply applications the ADA4937-1 is optimized for level-shifting, ground-referenced input signals. as such, the center of the input common-mode range is shifted approximately 1 v down from midsupply. for 5 v single-supply operation, the input common-mode range at the summing nodes of the amplifier is 0.3 v to 3.0 v, and 0.3 v to 1.9 v with a 3.3 v supply. to avoid clipping at the outputs, the voltage swing at the +in and Cin terminals must be confined to these ranges. setting the output common-mode voltage the v ocm pin of the ADA4937-1 is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on v+ and v?). relying on this internal bias results in an output common-mode voltage that is within about 100 mv of the expected value. in cases where more accurate control of the output common- mode level is required, it is recommended that an external source, or resistor divider (10 k or greater resistors), be used. the output common-mode offset listed in the specifications section assumes that the v ocm input is driven by a low impedance voltage source.
ADA4937-1 rev. 0 | page 20 of 28 it is also possible to connect the v ocm input to a common-mode level (cml) output of an adc. however, care must be taken to assure that the output has sufficient drive capability. the input impedance of the v ocm pin is approximately 10 k. if multiple ADA4937-1 devices share one reference output, it is recommended that a buffer be used. table 9 and table 10 list several common gain settings, associated resistor values, input impedance, output noise density, and approximate large signal bandwidth for both balanced and unbalanced input configurations. also shown are the input common-mode voltage swings under the given conditions for different v ocm settings with single 5 v and 3.3 v supplies. note that some gain configurations at 3.3 v cause the input common-mode voltage to exceed the specified range and should be avoided. if larger gains are required, other alternatives should be considered, such as an input common-mode offset, ac coupling, or a bipolar power supply. table 9. differential ground-referenced input, dc-coupled; see figure 48 common-mode swing at +in, ?in (v) +v s = 5 v v out, dm = 2.0 v p-p +v s = 3.3 v v out, dm = 1.6 v p-p nominal gain (db) r f () r g () r in, dm () differential output noise density (nv/hz) approximate large-signal bandwidth (mhz) +v s = 5 v/3.3 v v ocm = 2.5 v v ocm = 3.2 v v ocm = 1.6 v v ocm = 1.8 v 0 200 200 400 5.8 1500/1100 0.75 to 1.75 1.10 to 2.10 0.40 to 1.20 0.50 to 1.30 348 348 696 6.7 3 280 200 400 7.2 1500/1100 0.69 to 1.40 0.98 to 1.69 0.39 to 1.04 0.46 to 1.04 348 249 498 7.6 6 200 100 200 8.0 1400/1100 0.58 to 1.08 0.82 to 1.32 0.33 to 0.73 0.40 to 0.80 348 174 348 9.0 10 316 100 200 11 800/700 0.44 to 0.76 0.61 to 0.92 out of range 0.31 to 0.56 348 110 220 12 12 402 100 200 14 500/500 0.37 to 0.62 0.51 to 0.76 out of range out of range 348 86.6 173 13 14 499 100 200 17 300/300 0.32 to 0.52 0.43 to 0.63 out of range out of range 348 69.8 140 16 table 10. single-ended ground-referenced input, dc-coupled, r s = 50 ; see figure 49 common-mode swing at +in, -in (v) +v s = 5 v v out,dm = 2.0 v p-p +v s = 3.3 v v out,dm = 1.6 v p-p nominal gain (db) r f () r g1 () r t () r in,cm () r g2 () 1 differential output noise density (nv/hz) approximate large-signal bandwidth (mhz) +v s = 5 v/3.3 v v ocm = 2.5 v v ocm = 3.2 v v ocm = 1.6 v v ocm = 1.8 v 0 200 200 61.9 267 226 5.5 1500/1100 0.75 to 1.75 1.13 to 2.26 0.40 to 1.30 348 348 56.2 464 374 6.5 out of range 3 280 200 60.4 282 226 6.8 1500/1100 0.71 to 1.52 1.03 to 1.83 0.39 to 1.04 0.48 to 1.13 348 249 59.0 351 274 7.3 6 200 100 75.0 150 130 7.0 1400/1100 0.66 to 1.31 0.94 to 1.59 0.37 to 0.89 0.45 to 0.97 348 174 61.9 261 200 8.4 10 316 100 73.2 161 130 9.7 800/700 0.52 to 0.93 0.73 to 1.14 0.30 to 0.63 0.36 to 0.69 348 110 69.8 177 140 10 12 402 100 71.5 167 130 12 500/500 0.45 to 0.77 0.62 to 0.94 out of range 0.31 to 0.57 348 86.6 76.8 144 118 11 14 499 100 71.5 171 130 14 300/300 0.39 to 0.65 0.53 to 0.79 out of range out of range 348 69.8 86.6 120 100 12 1 r g2 = r g1 + (r s ||r t )
ADA4937-1 rev. 0 | page 21 of 28 layout, grounding, and bypassing as a high speed device, the ADA4937-1 is sensitive to the pcb environment in which it operates. realizing its superior performance requires attention to the details of high speed pcb design. the first requirement is a solid ground plane that covers as much of the board area around the ADA4937-1 as possible. however, the area near the feedback resistors (r f ), gain resistors (r g ), and the input summing nodes (pin 2 and pin 3) should be cleared of all ground and power planes (see figure 50 ). this minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. 06591-052 figure 50. ground and power plane voiding in vicinity of r f and r g the power supply pins should be bypassed as close to the device as possible and directly to a nearby ground plane. high frequency ceramic chip capacitors should be used. it is recommended that two parallel bypass capacitors (1000 pf and 0.1 f) be used for each supply. the 1000 pf capacitor should be placed closer to the device. further away, low frequency bypassing should be provided, using 10 f tantalum capacitors from each supply to ground. signal routing should be short and direct to avoid parasitic effects. wherever complementary signals exist, a symmetrical layout should be provided to maximize balanced performance. when routing differential signals over a long distance, pcb traces should be close together, and any differential wiring should be twisted such that lo op area is minimized. this reduces radiated energy and makes the circuit less susceptible to interference.
ADA4937-1 rev. 0 | page 22 of 28 high performance adc driving the ADA4937-1 is ideally suited for broadband if applications. the circuit in figure 51 shows a front-end connection for an ADA4937-1 driving an ad9445 , 14-bit, 105 msps adc. the ad9445 achieves its optimum performance when driven differentially. the ADA4937-1 eliminates the need for a transformer to drive the adc and performs a single-ended- to-differential conversion and buffering of the driving signal. the ADA4937-1 is configured with a single 5 v supply and unity gain for a single-ended input to differential output. the 61.9 termination resistor, in parallel with the single-ended input impedance of 267 , provides a 50 termination for the source. the additional 26 (226 total) at the inverting input balances the parallel impedance of the 50 source and the termination resistor driving the noninverting input. the signal generator has a symmetric, ground-referenced bipolar output. the v ocm pin of the ADA4937-1 is left floating, allowing the internal divider to set the output common-mode voltage at midsupply. one-half of the common-mode voltage is fed back to the summing nodes, biasing Cin and + in at 1.25 v. for a common-mode voltage of 2.5 v, each ADA4937-1 output swings between 2.0 v and 3.0 v, providing a 2 v p-p differential output. the output of the amplifier is ac-coupled to the adc through a second-order, low-pass filter with a cutoff frequency of 100 mhz. this reduces the noise bandwidth of the amplifier and isolates the driver outputs from the adc inputs. the ad9445 is configured for a 2 v p-p full-scale input by connecting the sense pin to agnd, as shown in figure 51 . 06591-064 vin? vin+ 47pf 30nh 30nh 24.3 ? 24.3 ? 50? signal generator 226 ? 200 ? v ocm 5v ADA4937-1 + 61.9 ? 200? 200 ? 14 buffer t/h adc clock/ timing ref sense agnd 0.1f 0.1f ad9445 3.3v (a) avdd1 5v (a) avdd2 3.3v (d) drvdd figure 51. ADA4937-1 driving an ad9445, 14-bit, 105 msps adc
ADA4937-1 rev. 0 | page 23 of 28 the circuit in figure 53 shows a simplified front-end connection for an ADA4937-1 driving an ad9246 , 14-bit, 125 msps adc. the ad9246 achieves its optimum performance when driven differentially. the ADA4937-1 performs the single-ended-to- differential conversion, eliminating the need for a transformer to drive the adc. the ADA4937-1 is configured with a single 5 v supply and a gain of ~2 v/v for a single-ended input to differential output. the 76.8 termination resistor, in parallel with the single- ended input impedance of 137 , provides a 50 ac termination for the source. the additional 30 (120 total) at the inverting input balances the parallel ac impedance of the 50 source and the termination resistor driving the noninverting input. the signal generator has a symmetric, ground-referenced bipolar output. the v ocm pin of the ADA4937-1 is left unconnected; therefore, the internal pull-ups set the output common-mode voltage to midsupply. a portion of this is fed back to the summing nodes, biasing Cin and + in at 0.55 v. for a common-mode voltage of 2.5 v, each ADA4937-1 output swings between 2.0 v and 3.0 v, providing a 2 v p-p differential output. the output is ac-coupled to a single-pole, low-pass filter. this reduces the noise bandwidth of the amplifier and provides some level of isolation from the switched capacitor inputs of the adc. the ad9246 is set for a 2 v p-p full-scale input by connecting the sense pin to agnd. the inputs of the ad9246 are biased at 1 v by connecting the cml output, as shown in figure 53 . the circuit was tested with a ?1 dbfs signal at various frequencies. figure 52 shows a plot of the second and third harmonic distortion (hd2/hd3) vs. frequency. ? 75 ?80 ?85 ?90 ?95 ?100 0 120 80 40 100 60 20 harmonic distortion (dbc) frequency (mhz) 06591-065 hd2 hd3 g = +2 figure 52. hd2/hd3 for combination of ADA4937-1 and ad9246 adc 06591-058 1.8v drvdd avdd vin? vin+ ad9246 agnd cml sense d11 to d0 10pf 10f 10f 10f 33 ? 33 ? 200 ? 200 ? 50? v in 90? 90? 76.8 ? 5v ADA4937-1 + 200 ? 200 ? 50? 76.8 ? 10f figure 53. ADA4937-1 driving an ad9246, a 14-bit, 125 msps adc
ADA4937-1 rev. 0 | page 24 of 28 06591-066 1.8v drvdd avdd vin? vin+ ad9230 agnd cml d11 to d0 30pf 10pf 56nh 56nh 33 ? 33 ? 50? v in 226 ? 200 ? v ocm 3.3v ADA4937-1 + 59? 453 ? 453 ? figure 54. ADA4937-1 driving an ad9230, a 12-bit, 250 msps adc 3.3 v operation the ADA4937-1 provides excellent performance in 3.3 v single-supply applications. significant power savings can be realized when the ADA4937-1 is used in combination with a low voltage adc. the circuit in figure 54 is an example of the ADA4937-1 driving an ad9230 , 12-bit, 250 msps adc that is specified to operate with a single 1.8 v supply. the performance of the adc is optimized when it is driven differentially, making the best use of the signal swing available within the 1.8 v supply. the ADA4937-1 performs the single-ended-to-differential conversion, common-mode level-shifting, and buffering of the driving signal. the ADA4937-1 is configured with a single 3.3 v supply and a gain of 2 v/v for a single-ended input to differential output. the 59 termination resistor, in parallel with the single-ended input impedance of 306 , provides a 50 termination for the source. the additional 26 (226 total) at the inverting input balances the parallel impedance of the 50 source and termination resistor driving the noninverting input. the signal generator has a symmetric, ground-referenced bipolar output. the v ocm pin is connected to the cml output of the ad9230 , and sets the output common mode of the ADA4937-1 at 1.4 v. one-third of the output common-mode voltage of the amplifier is fed back to the summing nodes, biasing Cin and + in at ~ 0.5 v. for a common-mode voltage of 1.4 v, each ADA4937-1 output swings between 1.09 v and 1.71 v, providing a 1.25 v p-p differential output. a third-order, 125 mhz, low-pass filter between the ADA4937-1 and the ad9230 reduces the noise bandwidth of the amplifier and isolates the driver outputs from the adc inputs.
ADA4937-1 rev. 0 | page 25 of 28 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 55. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters ordering guide model temperature range package description pa ckage option ordering quantity branding ADA4937-1ycpz-r2 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 5,000 h1s ADA4937-1ycpz-rl 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 1,500 h1s ADA4937-1ycpz-r7 1 ?40c to +105c 16-lead lfcsp_vq cp-16-2 250 h1s 1 z = rohs compliant part.
ADA4937-1 rev. 0 | page 26 of 28 notes
ADA4937-1 rev. 0 | page 27 of 28 notes
ADA4937-1 rev. 0 | page 28 of 28 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06591-0-5/07(0)

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